1) Field of the Invention
This invention relates to a method of dry etching a polysilicon layer formed on a silicon oxide layer of a semiconductor device and more particularly, to the selection of etching gases for etching a polysilicon film on a silicon oxide layer on a silicon substrate with a gas plasma.
2) Description of the Prior Art
Plasma etch processes and apparatus are generally well known for etching materials for semiconductor device fabrication. The process begins with an application of a masking material, such as photoresist, to a silicon wafer. The masking pattern protects area of the wafer from the etch process. The wafer is then placed in a plasma reactor (i.e., etcher) and etched. Subsequent steps are determined by the type of device being fabricated.
A common silicon etch process is based on fluorine. When mixtures such as CF.sub.4 --O.sub.2 are dissociated in an electrical discharge, fluorine atoms are liberated and volatilize the silicon as SiF.sub.4. Nevertheless, these processes are isotropic, i.e., they etch in all directions at the same rate. Moreover, anisotropic or vertical etches in silicon are not observed when fluorine is the sole etchant.
For vertical (anisotropic) etches of silicon, the use of gas mixtures, such as C.sub.2 F.sub.6 --Cl.sub.2, is known. The C.sub.2 F.sub.6 serves as a source of "recombinants", such as C.sub.3. The recombinants suppress lateral etching (in the horizontal direction) by recombining with Cl atoms which have been adsorbed on the etched polysilicon sidewalls. Etching can proceed in the vertical direction (perpendicular to the wafer surface) because ion bombardment from the plasma suppresses the recombination mechanism.
Further, the selectivity of etch between polysilicon and an underlying gate oxide (poly:oxide selectivity) must be as high as possible minimize oxide loss. These two requirements, anisotropy and poly: oxide selectivity, could previously only be fulfilled with chlorine-based dry etching processes, as opposed to fluorine-containing plasmas that tend to etch isotropically and have poor selectivity of poly:oxide.
In addition to an etch step, most conventional processes include an overetch step. Overetching is necessary in order to ensure that no residues are left on the wafer. If etching was stopped at the "end point", as determined by optical emission from the plasma, only parts of the wafer would be completely etched while other parts would still be covered with remaining polysilicon. This is due to non-uniformity of both the initial polysilicon film thickness and the etch rate. Moreover, most of the current polysilicon dry processes use an overetch gas containing chloride, especially CCl.sub.4, which is harmful to the environment as an ozone destroying chemical.
FIG. 1 illustrates an acceptable polysilicon etch profile. Substrate 10 is covered by gate oxide 12, polysilicon gate 14, native oxide 17, and photoresist 18. The polysilicon gate 14 sidewall 16 is vertical; it is not "undercut" 15 as shown in FIG. 2, or does not have a "foot" 20 at the poly gate 14 base displayed in FIG. 3. Both undercutting and foot forming processes result from complicated etch (isotropic and anisotropic) and deposition reactions. For example, the undercutting can result from fast (enhanced) isotropic etching near the bottom of the layer. Foot formation can be caused by redeposition, which can have a higher rate at the bottom of a small etching region.
Today's submicron polysilicon (poly) gate patterning requires minimum etch bias and vertical polysilicon sidewall profiles (anisotropy). The etch process should not undercut the mask, and the poly line should not be narrower at the polyoxide interface than it is at the poly-mask interface.
To ensure the etch in commercial plasma mode polysilicon etchers do not create an undercut in the profile, Carbon tetrachloride (CCl.sub.4) is often used to form a polymer on the polysilicon sidewall which protects the sidewall from undercutting etch processes during the overetch step. If CCl.sub.4 is absent in the overetch step, the undercut is inevitable as shown in FIG. 2. Moreover, the greater the polysilicon gate undercut, the greater the failure rate of the VLSI MOS devices. Sidewall passivation effect during etching is described by S. Sze in his book, VLSI Technology, Second Edition, McGraw-Hill international Editions, New York, N.Y. c. 1988, p.200-204.
In a common industry practice performed to prevent "foot" formation on polysilicon gates, an overetch step including CCl.sub.4 is performed after the main etch step. The overetch consumes the foot as well as any residual polysilicon on the oxide surface. A typical process which is widely used for polysilicon etch in an AUTOETCH-490 LAM RESEARCH CORPORATION is:
TABLE 1 __________________________________________________________________________ Conventional CCl.sub.4 Polysilicon Etch Process For an AUTOETCH-490 Press- Spac- ure Power ing Flow rate/Gas Time STEP mTorr W cm sccm sec __________________________________________________________________________ Break Through 600 325 0.45 150/He - 175/C.sub.2 F.sub.6 20 Main Etch 375 223 0.45 200/HE - 80/Cl.sub.2 40 to 50 Overetch 375 223 0.45 200/HE - 80/Cl.sub.2 - 30/CCl.sub.4 30 __________________________________________________________________________
In order to produce polysilicon gates of proper dimensions using dry etch processes, it is necessary to form a deposit on the etching (polysilicon) side wall to protect the etching sidewall from ions and/or radicals in a plasma which can etch (laterally) the sidewall. The CCl.sub.4 gas in the conventional overetch step is used to form a polymer which protects the polysilicon sidewall 16 from undercut during the overetch step. If the overetch step is performed without a C containing reactant, no polymer is formed, and undercutting (15) results as shown in FIG. 2.
While the conventional CCl.sub.4 overetch step yields satisfactory polysilicon profiles, the CCl.sub.4 is an ozone destroying, CFC material. Because of the great environmental damage caused by chloride containing chemicals and worldwide government regulation of CFC emissions, there is a need to develop an overetch process that does not use a chloride reactant in the overetch step, but still yields satisfactory polysilicon etch profiles.
The following terms and abbreviations are or may be used herein: Polysilicon (poly); Carbon (C); Chlorine (Cl.sub.2); Helium (He); Hydrogen (H); milli Torr (mT or mTorr); standard cubic centimeters per minute (sccm); Angstroms (.ANG.); microns (.mu.m); watts (w); kilowatts (kW); Celsius (.degree. C.); etch rate (ER); seconds (sec); minutes (min.); hours (hr); less than (&lt;); greater than (&gt;); percent (%); ratio of one element "X" to another element "Y" (X:Y); fluoride is a compound of fluorine (F); and chloride is a compound of chlorine (Cl).
U.S. Pat. No. 5,296,095 to Nabeshhima et al. teaches a process for etching silicon oxide using a principle etching gas and an additive gas--the etching gas compound contains a C element or an S element or a Cl element together with an F element (such as CF.sub.4), and the additive gas compound contains a C element and two or more H elements (such as CH.sub.2 F.sub.2, CHF.sub.3 or CH.sub.3 Br).
U.S. Pat. No. 4,808,259 to Jillie, Jr. et al. teaches a method for etching of MOS devices (SiO.sub.2, Si.sub.3 N.sub.4, and oxynitride (ONO) utilizing a multi-step power reduction plasma etching recipe to reduce ion bombardment damage on the resulting surface.
U.S. Pat. No. 5,180,464 to Tatsumi et al. teaches a dry etch method to etch a polycide film using an etching gas containing a fluorine gas mixed with at least HBr.
U.S. Pat. No. 5,188,980 to Lai teaches a process for dry etching a multilayer tungsten silicide gate structure where three steps are used: 1) a plasma etch using a mixture of chlorine and helium gases, 2) a helium purge, and 3) an final etch using chlorine and helium gases. This processes aims to reduce undercutting of the polycide layer.
U.S. Pat. No. 5,242,536 to Schoenborn discloses an anisotropic polysilicon etch process using Cl.sub.2 /HBr/He. The use of HBr allows operation under high poly: oxide selectivity conditions that would otherwise produce lateral etching of poly under the photoresist mask isotropy). The selectivity poly:resist ratio is increased by including HBr. The use of HBr appears to enhance poly sidewall passivation without relying on resist redeposition. In contrast thereto, in the present invention HBr is not used. In the present invention, a fluoride containing gas such as C.sub.2 F.sub.6 is used in a passivation step, prior to the overetch step to suppress sidewall undercutting.
The patents described above do not resolve the problem of providing acceptable polysilicon profiles without using CCl.sub.4 in the overetch step. Neither do they solve the limitation that etching tends to become more isotropic during overetch, when the underlying oxide is exposed, resulting in undercutting. Furthermore, more accurate polysilicon profiles are desirable.